搜索资源列表
multiplier
- 个人收集的各种乘法器vhdl源代码,都经过验证,可以直接使用的。-Collected a lot of multiplier vhdl source code
bit4_mul
- vhdl写的程序,并行4位乘法器 加快流据传递,提高算法效率-bit4_mul
chfqi
- 简易5位乘法器的设计 用于EDA课程设计和VHDL的入门学习-Easy 5 Multiplier for EDA VHDL introduction to course design and learning
12bitMulti
- 用VHDL编写的有符号的12位乘法器,编译通过,仿真正确,FPGA开发板上用过的。-Prepared using VHDL signed 12-bit multiplier, compile, correct simulation, FPGA development board used.
multi8x8
- 用VHDL设计应用移位相加原理的8位乘法器,使用QuartusII仿真验证。-VHDL design applications with the principle of adding 8-bit shift multiplier, using QuartusII simulation.
Using_Embedded_Multipliers_in_Spartan-3_FPGAs
- 使用Spartan-3的嵌入式乘法器,VHDL语言-Using Embedded Multipliers in Spartan-3 FPGAs
multiply
- vhdl语言编写,实现了任意位数的两个数的乘法器-Realize any two-digit number of multiplier
mul32
- 32位无符号乘法器 采用VHDL语言编写,很容易改为有符号32位乘法器-32-bit unsigned multiplier using VHDL language, it is easy to signed 32-bit multiplier
MULTIPLIER
- 基于VHDL硬件描述语言设计的乘法器,位数可以修改-VHDL hardware descr iption language based on the design of the multiplier, the median can be modified
4X
- VHDL实现的4位乘法器,绝对好用,libero8.5仿真没问题!-VHDL implementation of the 4-bit multiplier
Multiplier
- VHDL语言设计的乘法器,经过试验箱测试通过,用试验箱的8个拨码开关输入数字,按键按下输出结果。-VHDL language design of multiplier, after chamber test, with the chamber of the 8 DIP switch input numbers, key press output.
8bit-Shift-and-Adder--multiplier
- 8位乘法器,经移位相加算法来实现的,用的VHDL语言-8-bit multiplier, adding the algorithm to realize the shift of
mult
- 自己编写的乘法器 二进制4*4 vhdl环境 仿真通过-On time-multiplier binary imagecut.rar 4* 4 VHDL environmental simulation through
95637012Multiplier
- 一种可以完成16位有符号/无符号二进制数乘法的乘法器。该乘法器采用了改进的booth算法,简化了部分积的符号扩展,采用Wallace树和超前进位加法器来进一步提高电路的运算速度。本乘法器可以作为嵌入式CPU内核的乘法单元,整个设计用VHDL语言实现。- This file contains all the entity-architectures for a complete-- k-bit x k-bit Booth multiplier.-- the design makes use of
multiplierunit
- VHDL/FPGA/Verilog 实现乘法器的功能-use VHDL/FPGA/Verilog multiplier unit
mult
- 4比特乘法器的vhdl实现,含modelsim测试文件-4-bit multiplier vhdl implementation, including the test file modelsim
butterfly1
- FFT 蝶形处理器的VHDL代码,由一个加法器,一个减法器和一个实例化为组件的旋转因子乘法器ccmul组成-FFT butterfly processor VHDL code by an adder, a subtracter, and an instance of the component into the composition of the rotation factor multiplier ccmul
mult
- 4级流水乘法器,本文利用FPGA完成了基于半加器、全加器、进位保留加法器的4比特流水乘法器的设计,编写VHDL程序完成了乘法器的功能设计,并通过Modelsim进行了仿真验证。-Four water multipliers, this paper complete FPGA-based half adder, full adder, carry-save adder 4 bit pipeline multiplier design, write VHDL program to complete
shift_mult_4
- 四位移位乘法器 VHDL 代码 已验证,可以直接拿来用-Four shift multiplier VHDL code has been verified, can be directly used
4MUL
- 四位并行乘法器的VHDL源代码,已通过验证,可以使用-Four parallel multiplier VHDL source code has been validated, you can use